Impact of the hardened floating-point cores on HIL technology

The Hardware-In-the-Loop (HIL) technique is increasingly used for testing power electronics. FPGAs (Field-Programmable Gate Array) are becoming usual in this kind of emulation due to their acceleration capabilities. But even using FPGAs, it has not been possible to reach real time simulations when small integration steps are necessary (around 100 ns or lower) if floating-point representation is used. Fixed-point has been the solution, but at a high design effort cost. With the release of FPGAs with HFP (Hardened Floating-Point) cores – dedicated floating-point blocks implemented in silicon – the minimum achievable simulation step decreases significantly. This paper presents a comparison between HFP cores, floating-point in programmable logic and fixed-point for HIL models. Results show that both HFP-based and fixed-point arithmetic achieve a simulation step around 10 ns for a full-bridge converter model. A comparison regarding resolution and accuracy is also presented, because acceleration is not the only issue when decreasing the integration step. Numerical resolution also plays an important role, and 32-bit floating-point representation finds a double barrier: acceleration marked by technology, and numerical resolution. Both are explored in this paperThis work has been supported by the Spanish Ministerio deEconomía y Competitividad under project TEC2013-43017-

Parametrizable fixed-point arithmetic for HIL with small simulation steps

Hardware-in-the-loop (HIL) techniques are increasingly used for test purposes because of their advantages over classical simulations. Field-programmable gate arrays (FPGAs) are becoming popular in HIL systems because of their parallel computing capabilities. In most cases, FPGAs are mainly used for signal processing, such as input pulsewidth modulation sampling and conditioning, while there are also processors to model the system. However, there are other HIL systems that implement the model in the FPGA. For FPGA implementation and regarding the arithmetics, there are two main possibilities: fixed-point and floating-point. Fixed-point is the best choice only when real-time simulations with small simulation steps are needed, while floating point is the common choice because of its flexibility and ease of use. This paper presents a novel hybrid arithmetic for FPGAs called parametrizable fixed-point which takes advantage of both arithmetics as the internal operations are accomplished using simple signed integers, while the point location of the variables can be adjusted as necessary without redesigning the model of the plant. The experimental results show that a buck converter can be modeled using this novel arithmetic with a simulation step below 20 ns. Besides, the experiments prove that the proposed model can be adjusted to any set of values (voltages, currents, capacitances, and so on.) keeping its accuracy without resynthesizing, showing the big advantage over the fixed-point arithmeticThis work has been supported by the Spanish Ministerio de Economía y Competitividad under project TEC2013-43017-

Modeling of deadtime events in power converters with half-bridge modules for a highly accurate hardware-in-the-loop fixed point implementation in fpga

Hardware-in-the-loop (HIL) simulations of power converters must achieve a truthful representation in real time with simulation steps on the order of microseconds or tens of nanoseconds. The numerical solution for the differential equations that model the state of the converter can be calculated using the fourth-order Runge–Kutta method, which is notably more accurate than Euler methods. However, when the mathematical error due to the solver is drastically reduced, other sources of error arise. In the case of converters that use deadtimes to control the switches, such as any power converter including half-bridge modules, the inductor current reaching zero during deadtimes generates a model error large enough to offset the advantages of the Runge–Kutta method. A specific model is needed for such events. In this paper, an approximation is proposed, where the time step is divided into two semi-steps. This serves to recover the accuracy of the calculations at the expense of needing a division operation. A fixed-point implementation in VHDL is proposed, reusing a block along several calculation cycles to compute the needed parameters for the Runge–Kutta method. The implementation in a low-cost field-programmable gate arrays (FPGA) (Xilinx Artix-7) achieves an integration time of 1 µs. The calculation errors are six orders of magnitude smaller for both capacitor voltage and inductor current for the worst case, the one where the current reaches zero during the deadtimes in 78% of the simulated cycles. The accuracy achieved with the proposed fixed point implementation is very close to that of 64-bit floating point and can operate in real time with a resolution of 1 µs. Therefore, the results show that this approach is suitable for modeling converters based on half-bridge modules by using FPGAs. This solution is intended for easy integration into any HIL system, including commercial HIL systems, showing that its application even with relatively high integration steps (1 µs) surpasses the results of techniques with even faster integration steps that do not take these events into accoun

Spatial fluctuations in an optical parametric oscillator below threshold with an intracavity photonic crystal

We show how to control spatial quantum correlations in a multimode, degenerate, type-I optical parametric oscillator below threshold by introducing a spatially inhomogeneous medium, such as a photonic crystal, in the plane perpendicular to light propagation. We obtain the analytical expressions for all of the correlations in terms of the relevant parameters of the problem and study the number of photons, entanglement, squeezing, and twin beams. Considering different regimes and configurations, we show that it is possible to tune the instability thresholds as well as the quantumness of correlations by breaking the translational invariance of the system through a photonic-crystal modulation. © 2012 American Physical Society.We acknowledge financial support from the MICINN (Spain) and FEDER (EU) through projects FIS2007-60327 (FISICOS) and FIS2011-23526 (TIQS), from CSIC through project CoQuSys (200450E566) and from the Govern Balear through project AAEE0113/09. MAGM acknowledges sup- port from the Spanish Ministry of Science and Education (MEC) and the US Fulbright CommissionPeer Reviewe

Analysis of the aliasing effect caused in hardware-in-the-loop when reading PWM inputs of power converters

Hardware-in-the-loop (HIL) systems are commonly used to debug controllers in closed-loop operation. Therefore, the frequency response of the emulated subsystem is of special relevance. Undesirable oscillations can appear as a consequence of digitally sampling the switch control signals in power converter HIL models. These oscillations at relatively low frequencies, below the switching frequency, may confound the closed-loop operation and, therefore, the appropriate debugging of the controller. This paper shows that the lost information when an HIL model reads a PWM signal may create some output offset error or steady-state fluctuations, especially when the switching period and the sampling step get closer. The aliasing frequencies produced by the input sampling are calculated, and the small-signal analysis explains the relation between the output oscillation and the input PWM sub-harmonics. The output error spectrum proves that the main error sub-harmonics have the same aliasing frequency components. Both captured oscilloscope results obtained by an NI myRIO device and MATLAB simulations verify that significant distortions can be seen in the output inductor current if there is a low aliasing frequency in the digital version of the input PWM signal read by the HIL mode

Evaluation of the different numerical formats for HIL models of power converters after the adoption of VHDL-2008 by xilinx

Hardware in the loop is a widely used technique in power electronics, allowing to test and debug in real time (RT) at a low cost. In this context, field-programmable gate arrays (FPGAs) play an important role due to the high-speed requirements of RT simulations, in which area optimization is also crucial. Both characteristics, area and speed, are affected by the numerical formats (NFs) and their rounding modes. Regarding FPGAs, Xilinx is one of the largest manufacturers in the world, offering Vivado as its main design suite, but it was not until the release of Vivado 2020.2 that support for the IEEE NF libraries of VHDL-2008 was included. This work presents an exhaustive evaluation of the performance of Vivado 2020.2 in terms of area and speed using the native IEEE libraries of VHDL-2008 regarding NF. Results show that even though fixed-point NFs optimize area and speed, if a user prefers the use of floating-point NFs, with this new release, it can be synthesized—which could not be done in previous versions of Vivado. Although support for the native IEEE libraries of VHDL-2008 was included in Vivado 2020.2, it still lacks some issues regarding NF conversion during synthesis while support for simulation is not yet includedThis research received no external fundin

Comparison of different design alternatives for hardware-in-the-loop of power converters

This paper aims to compare different design alternatives of hardware-in-the-loop (HIL) for emulating power converters in Field Programmable Gate Arrays (FPGAs). It proposes various numerical formats (fixed and floating-point) and different approaches (pure VHSIC Hardware Description Language (VHDL), Intellectual Properties (IPs), automated MATLAB HDL code, and High-Level Synthesis (HLS)) to design power converters. Although the proposed models are simple power electronics HIL systems, the idea can be extended to any HIL system. This study compares the design effort of different coding methods and numerical formats considering possible synthesis tools (Precision and Vivado), and it comprises an analytical discussion in terms of area and speed. The different models are synthesized as ad-hoc modules in general-purpose FPGAs, but also using the NI myRIO device as an example of a commercial tool capable of implementing HIL models. The comparison confirms that the optimum design alternative must be chosen based on the application (complexity, frequency, etc.) and designers’ constraints, such as available area, coding expertise, and design effor

Distribuição de sementes por uma semeadora puncionadora para agricultura familiar

Family farming seeks to use less-aggressive agricultural practices, however, there is little machinery available that is suitable for the reality of this sector. This has led to the use of technically incorrect practices, which have contributed to the impoverishment, compaction and desertification of agricultural soils. Punch seeders are seen as a promising alternative for carrying out sowing in family farming, as they employ localised seed distribution with less disturbance of the soil and the consequent preservation and conservation of its structure. The aim of this study was to evaluate the quality of seed distribution by a punch seeder used in family farming. The experiment was carried out in a soil classified as a Red-Yellow Argisol. Descriptive statistics were used to evaluate the quality of seed distribution by the punch system. Statistical Process Control was adopted to evaluate quality control in the seed distribution process. The results showed that the performance of the punch seeder was similar to that of the precision pneumatic seeder, with 90.2% acceptable spacing. As demonstrated by the SPC study that showed the process to be compatible with quality standards, the punch seeder is therefore a viable alternative in the sowing process for family farming, since an improvement in sowing quality, with a precision of 88.4% was obtained. The punch system resulted in less soil disturbance when compared to the disc harrow and manual seeder, and proved to be an effective solution for conservation agriculture.503502509COORDENAÇÃO DE APERFEIÇOAMENTO DE PESSOAL DE NÍVEL SUPERIOR - CAPESSem informaçãoA agricultura familiar busca utilizar práticas agrícolas menos agressivas, entretanto existem poucas máquinas adequadas à realidade deste segmento, isso tem levado ao uso de práticas tecnicamente incorretas, que vem contribuindo para o empobrecimento, compactação e desertificação dos solos agrícolas. Diante disso, as semeadoras puncionadoras apresentam-se como uma possibilidade promissora para realizar o processo de semeadura para agricultura familiar, visto que realiza a distribuição de semente de forma pontual, contribuindo para a menor mobilização do solo e consequente preservação e conservação da estrutura do mesmo. O objetivo do trabalho foi avaliar a qualidade de distribuição de sementes por uma semeadora puncionadora para a agricultura familiar. O ensaio foi realizado em um solo classificado como Argissolo Vermelho-amarelo. Foi utilizada a estatística descritiva para avaliar a qualidade da distribuição de sementes pelo sistema puncionador. O Controle Estatístico do Processo foi adotado para avaliar o controle de qualidade do processo de distribuição de sementes. Os resultados demostraram que a semeadora puncionadora apresentou desempenho semelhante à semeadora de precisão pneumática, obtendo 90,2% de espaçamentos aceitáveis, sendo uma alternativa viável para realizar o processo de semeadura para a agricultura familiar, fato comprovado pelo estudo do CEP que indicou a adequação do processo de semeadura aos padrões de qualidade, pois obteve 88,4% de precisão no processo, possibilitando a elevação da qualidade de semeadura. O sistema puncionador proporcionou menor mobilização do solo quando comparado ao sulcador de disco e semeadora manual, mostrando-se como uma solução eficaz para a agricultura conservacionista